DDC Design Project
MILESTONE 3 - AFTER PEY
PEY AT POWER SYSTEMS PERFORMANCE,
IBM CANADA
APPLIED ELECTRICAL AND COMPUTER SCIENCE
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 Ubuntu and RHEL were the main operating systems for servers due to their superior performance and open source nature. |  This is a vital component of running apache spark on multiple server nodes. A distributed file system that allows massive data sets to be pieced and split to multiple servers but still treated like one data set. |
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 An in-memory map reduce computation library. It leverages superior memory I/O to perform faster computations on large data sets across multiple servers. |  The power 8 server came into the market in 2015 with SMT 8 cores and superior memory access speed compared to the Intel Haswell. |
 By understanding the Power 8 architecture and its interaction with Spark, we improve the performance of the software using Java and architectural level configurations. |
Date: August 5th, 2016
Description: During PEY, I learned to function both autonomously and as part of a team. The team had a very well defined problem in a limited scope (optimize Apache Spark's performance on Power 8 until it is faster than on Haswell), but it takes deep understanding of the Power 8 server's architecture to succeed. I felt the design space for the work was very limited and different from what I imagined.
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The reason I avoided applications on phones and computers was because they felt limiting. After working in a limited design space the entire PEY, I wanted to explore a more applicable and open design concepts where I helped define the design space. The DDC project was offering that. Drone attachments and designs were a new and innovative field with hundreds of different models and attachments coming out every year. By working on the DDC project, I would be gaining insight into the UAV industry as well as the MIE design mindset.
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Improvement: Teamwork, Technical Communication, Application of Knowledge, Independent Learning
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Strengths: Experimental practice, Detail Oriented, Textual Analysis, Writing, Work Organization
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Known Weaknesses: Engineering design methodology, Inter-Disciplinary Cooperation, Time Organization, Project Organization,
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Unknown Weaknesses: Depth of Technical Skills
Goal: Gain new perspective on working with MIE on design projects, as well as, practicing effectively inter-disciplinary communication and teamwork.
 Learning the timing and component level functions of BJTs and MOSFETs as well as the lower level parasitic capacitance and transistor layouts. |  Learning the top level view of how page tables, locking, caches, and threads connect the processor with the memory and improve performance. |
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 Designed a 4096B, VLSI computation chip in a CAD tool, and tested its functionality. |  Above is a shortest-path algorithm. The course goal is to learn to design efficient algorithms which target a reduction in the Big O notation and avoiding exponentially complex solutions. |